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| INTEGRATED CIRCUITS PDI1394P22 3-port physical layer interface Objective specification 1999 Jul 09 Philips Semiconductors Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 1.0 FEATURES * Fully supports provisions of IEEE 1394-1995 Standard for high performance serial bus and the P1394a supplement (Version 2.0)1 * Supports extended bias-handshake time for enhanced interoperability with camcorders * Full P1394a support includes: - Connection debounce - Arbitrated short reset - Multispeed concatenation - Arbitration acceleration - Fly-by concatenation - Port disable/suspend/resume * Interface to link-layer controller supports low-cost bus-holder isolation and optional Annex J electrical isolation * Data interface to link-layer controller through 2/4/8 parallel lines at 49.152 MHz * Low-cost 24.576 MHz crystal provides transmit, receive data at 100/200/400 Mbits/s, and link-layer controller clock at 49.152 MHz * Provides three 1394a fully-compliant cable ports at 100/200/400 Megabits per second (Mbits/s) * Does not require external filter capacitors for PLL * Interoperable with link-layer controllers using 3.3 V and 5 V supplies * Fully compliant with Open HCI requirements * Cable ports monitor line conditions for active connection to remote node. * Interoperable with other Physical Layers (PHYs) using 3.3 V and 5 V supplies * Power down features to conserve energy in battery-powered applications include: - Automatic device power down during suspend - Device power down terminal - Link interface disable via LPS - Inactive ports powered-down * Node power class information signaling for system power management * Cable power presence monitoring * Separate cable bias (TPBIAS) for each port * Register bits give software control of contender bit, power class bits, link active bit, and 1394a features * Logic performs system initialization and arbitration functions * Encode and decode functions included for data-strobe bit level encoding * Fully interoperable with FireWireTM implementation of IEEE Std 1394 * Function and pin compatible with the Lucent FW803 400 Mbps Phy 2.0 DESCRIPTION The PDI1394P22 provides the digital and analog transceiver functions needed to implement a three port node in a cable-based IEEE 1394-1995 and/or 1394a network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The PDI1394P22 is designed to interface with a Link Layer Controller (LLC), such as the PDI1394L11 or PDI1394L21. * Incoming data resynchronized to local clock * Single 3.3 volt supply operation * Minimum VDD of 2.7 V for end-of-wire power-consuming devices * While unpowered and connected to the bus, will not drive TPBIAS on a connected port, even if receiving incoming bias voltage on that port 3.0 ORDERING INFORMATION PACKAGE 64-pin plastic LQFP TEMPERATURE RANGE 0C to +70C OUTSIDE NORTH AMERICA PDI1394P22 BD NORTH AMERICA PDI1394P22 BD PKG. DWG. # SOT314-2 1. Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited. 1999 Jul 09 2 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 4.0 PIN CONFIGURATION SYSCLK PLLGND PLLVDD /RESET DGND DGND AGND AGND DVDD AVDD 64 LREQ DGND CTL0 CTL1 D0 D1 DVDD D2 D3 D4 D5 D6 D7 DGND CNA LPS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DVDD 63 62 61 60 59 58 57 56 55 54 53 52 51 50 AVDD R1 R0 XI 49 48 47 46 45 44 43 42 41 TPBIAS2 TPA2+ TPA2- TPB2+ TPB2- AVDD TPBIAS1 TPA1+ TPA1- TPB1+ TPB1- TPBIAS0 TPA0+ TPA0- TPB0+ TPB0- PDI1394P22 AGND 40 39 38 37 36 35 34 33 32 AGND 18 C/LKON XO 19 PD 20 PC0 21 PC1 22 PC2 23 /ISO 24 CPS 25 DGND 26 DVDD 27 DVDD 28 TEST1 29 TEST0 30 AVDD 31 AVDD SV001782 5.0 PIN DESCRIPTION Name AGND AVDD Pin Type Supply Supply Pin Numbers 32, 49, 52, 53 30, 31, 43, 50, 51 I/O -- -- Description Analog circuit ground terminals. These terminals should be tied together to the low impedance circuit board ground plane. Analog circuit power terminals. A combination of high frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10 F filtering capacitors are also recommended. These supply terminals are separated from PLLVDD and DVDD internal to the device to provide noise isolation. They should be tied at a low impedance point on the circuit board. Cable Not Active output. This terminal is asserted high when there are no ports receiving incoming bias voltage. Cable Power Status input. This terminal is normally connected to cable power through a 370-410 k resistor. This circuit drives an internal comparator that is used to detect the presence of cable power. Control I/Os. These bi-directional signals control communication between the PDI1394P22 and the LLC. Bus holders are built into these terminals. CNA CPS CMOS CMOS 15 24 O I CTL0, CTL1 CMOS 5V tol 3, 4 I/O 1999 Jul 09 3 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 Name C/LKON Pin Type CMOS 5V tol 18 Pin Numbers I/O I/O Description Bus Manager Contender programming input and link-on output. On hardware reset, this terminal is used to set the default value of the contender status indicated during self-ID. Programming is done by tying the terminal through a 10k resistor to a high (contender) or low (not contender). The resistor allows the link-on output to override the input. Following hardware reset, this terminal is the link-on output, which is used to notify the LLC to power-up and become active. The link-on output is a square-wave signal with a period of approximately 163 ns (8 SYSCLK cycles) when active. The link-on output is deasserted low when the LPS input terminal is active. DGND D0-D7 DVDD Supply CMOS 5V tol Supply 2, 14, 25, 56, 64 5, 6, 8, 9, 10, 11, 12, 13 7, 17, 26, 27, 62 -- I/O -- Digital circuit ground terminals. These terminals should be tied together to the low impedance circuit board ground plane. Data I/Os. These are bi-directional data signals between the PDI1394P22 and the LLC. Bus holders are built into these terminals. Digital circuit power terminals. A combination of high frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10 F filtering capacitors are also recommended. These supply terminals are separated from PLLVDD and AVDD internal to the device to provide noise isolation. They should be tied at a low impedance point on the circuit board. Link interface isolation control input. This terminal controls the operation of output differentiation logic on the CTL and D terminals. If an optional isolation barrier of the type described in Annex J of IEEE Std 1394-1395 is implemented between the PDI1394P22 and LLC, the /ISO terminal should be tied low to enable the differentiation logic. If no isolation barrier is implemented (direct connection), or bus holder isolation is implemented, the /ISO terminal should be tied high to disable the differentiation logic. Link Power Status input. This terminal is used to monitor the power status of the LLC, and is connected to either the VDD supplying the link layer controller through a 1k resistor, or to a pulsed output which is active when the LLC is powered. The pulsed output is useful when using an isolation barrier. If this input is low for more than 25 ms, the LLC is considered powered down. If this input is high for more than 20 ns, the LLC is considered powered up. If the LLC is powered-down, the PHY-LLC interface is disabled, and the PDI1394P22 performs only the basic repeater functions required for network initialization and operation. Bus holder is built into this terminal. LLC Request input. The LLC uses this input to initiate a service request to the PDI1394P22. Bus holder is built into this terminal. Power Class programming inputs. On hardware reset, these inputs set the default value of the power class indicated during self-ID. Programming is done by tying the terminals high or low. Refer to Table 18 for encoding. Power Down input. A logic high on this terminal turns off all internal circuitry except the cable-active monitor circuits which control the CNA output. Bus holder is built into this terminal. For more information, refer to Section 17.3 PLL circuit ground terminals. These terminals should be tied together to the low impedance circuit board ground plane. PLL circuit power terminals. A combination of high frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 F and 0.001 F. Lower frequency 10 F filtering capacitors are also recommended. These supply terminals are separated from DVDD and AVDD internal to the device to provide noise isolation. They should be tied at a low impedance point on the circuit board. Logic reset input. Asserting this terminal low resets the internal logic. An internal pull-up resistor to VDD is provided so only an external delay capacitor in parallel with a resistor is required for proper power-up operation. For more information, refer to Section 17.3. This input is otherwise a standard logic input, and can also be driven by an open-drain type driver. 4 /ISO CMOS 23 I LPS CMOS 5V tol 16 I LREQ PC0, PC1, PC2 CMOS 5V tol CMOS 5V tol 1 20, 21, 22 I I PD CMOS 5V tol 19 I PLLGND PLLVDD Supply Supply 58 57 -- -- /RESET CMOS 5V tol 61 I 1999 Jul 09 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 Name R0, R1 Pin Type Bias Pin Numbers 54, 55 I/O -- Description Current setting resistor terminals. These terminals are connected to an external resistance to set the internal operating currents and cable driver output currents. A resistance of 6.34 k 1% is required to meet the IEEE Std 1394-1995 output voltage limits. System clock output. Provides a 49.152 MHz clock signal, synchronized with data transfers, to the LLC. Test control input. This input is used in manufacturing tests of the PDI1394P22. For normal use, this terminal should be tied to GND. Test control input. This input is used in manufacturing tests of the PDI1394P22. For normal use, this terminal should be tied to GND. Twisted-pair cable A differential signal terminals. Board traces from each g g pair of positive and negative differential signal terminals should be kept matched and as short as possible to the external load resistors and to the cable connector. SYSCLK TEST0 TEST1 TPA0+, TPA1+, TPA2+ TPA0-, TPA1-, TPA2- TPB0+, TPB1+, TPB2+ TPB0-, TPB1-, TPB2- TPBIAS0, TPBIAS1, TPBIAS2 CMOS CMOS CMOS Cable 63 29 28 36, 41, 47 O I I I/O Cable 35, 40, 46 I/O Cable 34, 39, 45 I/O Twisted-pair cable B differential signal terminals. Board traces from each pair of positive and negative differential signal terminals should be kept g g matched and as short as possible to the external load resistors and to the cable connector. Twisted-pair bias output. This provides the 1.86V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection. Each of these terminals must be decoupled with a 0.3 F-1 F capacitor to ground. Crystal oscillator inputs. These terminals connect to a 24.576 MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used. Can also be driven by an external clock generator (leave XO unconnected in this case). Cable 33, 38, 44 I/O Cable 37, 42, 48 I/O XO, XI Crystal 60, 59 -- 1999 Jul 09 5 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 6.0 BLOCK DIAGRAM CPS LPS /ISO C/LKON RECEIVED DATA DECODER/ RETIMER CABLE POWER DETECTOR CPS SYSCLK LREQ CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 PC0 PC1 PC2 CNA CABLE PORT 0 LINK INTERFACE I/O TPA0+ TPA0- ARBITRATION AND CONTROL STATE MACHINE LOGIC TPB0+ TPB0- TPA1+ TPA1- CABLE PORT 1 TPB1+ TPB1- TPA2+ TPA2- TPB2+ TPB2- R0 R1 TPBIAS0 TPBIAS1 TPBIAS2 CABLE PORT 2 BIAS VOLTAGE AND CURRENT GENERATOR CRYSTAL OSCILLATOR, PLL SYSTEM, AND CLOCK GENERATOR TRANSMIT DATA ENCODER XI XO PD /RESET SV01743 7.0 FUNCTIONAL SPECIFICATION The PDI1394P22 requires only an external 24.576 MHz crystal as a reference. An external clock can be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216 MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded Strobe and Data information. A 49.152 MHz clock signal, supplied to the associated LLC for synchronization of the two chips, is used for resynchronization of the received data. The Power Down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL and disables all circuits except the cable bias detectors at the TPB terminals. The port transmitter circuitry and the receiver circuitry are also disabled when the port is disabled, suspended, or disconnected. The PDI1394P22 supports an optional isolation barrier between itself and its LLC. When the /ISO input terminal is tied high, the LLC interface outputs behave normally. When the /ISO terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in IEEE 1394a section 5.9.4. To operate with single capacitor (bus holder) isolation, the /ISO on the PHY terminal must be tied high. Data bits to be transmitted through the cable ports are received from the LLC on two, four or eight parallel paths (depending on the requested transmission speed). They are latched internally in the PDI1394P22 in synchronization with the 49.152 MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304/196.608/392.216 Mbits/s (referred to as S100, S200, and S400 speed, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s). During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial 1999 Jul 09 6 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 data bits are split into two-, four- or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152 MHz system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission (speed signalling). In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage (cable bias detection). The PDI1394P22 provides a 1.86 V nominal bias voltage at the TPBIAS terminal for port termination. the PHY contains three independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 0.3 F-1 F. The line drivers in the PDI1394P22 operate in a high-impedance current mode, and are designed to work with external 112 line-termination resistor networks in order to match the 110 cable impedance. One network is provided at each end of all twisted-pair cable. Each network is composed of a pair of series-connected 56 resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B terminals is coupled to ground through a parallel R-C network with recommended values of 5 k and 220 pF. The values of the external line termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current setting resistor has a value of 6.34 k 1%. When the power supply of the PDI1394P22 is removed while the twisted-pair cables are connected, the PDI1394P22 transmitter and receiver circuitry presents a high impedance to the cable in order to not load the TPBIAS voltage on the other end of the cable. When the PDI1394P22 is used with one or more of the ports not brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and TPB- terminals can be tied together and then pulled to ground, or the TPB+ and TPB- terminals can be connected to the suggested termination network. The TPA+ and TPA- and TPBIAS terminals of an unused port can be left unconnected. The TEST0 and TEST1 terminals are used to set up various manufacturing test conditions. For normal operation, the TEST0 and TEST1 terminals should be connected to ground. Four package terminals, used as inputs to set the default value for four configuration status bits in the self-ID packet, should be hard-wired high or low as a function of the equipment design. The PC0-PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 18 for power class encoding. The C/LKON terminal is used as an input to indicate that the node is a contender for bus manager. The PHY supports suspend/resume as defined in the IEEE 1394a specification. The suspend mechanism allows pairs of directly connected ports to be placed into a low power state while maintaining a port-to-port connection between 1394 bus segments. While in a low power state, a port is unable to transmit or receive data transaction packets. However, a port in a low power state is capable of detecting connection status changes and detecting incoming TPBIAS. When all three ports of the PDI1394P22 are suspended, all circuits except the bias-detection circuits are powered down, resulting in significant power savings. The TPBIAS circuit monitors the value of incoming TPA pair common-mode voltage when local TPBIAS is inactive. Because this circuit has an internal current source and the connected node has a current sink, the monitored value indicates the cable connection status. This monitor is called connect-detect. Both the cable bias-detect monitor and TPBIAS connect-detect monitor are used in suspend/resume signaling and cable connection detection. For additional details of suspend/resume operation, refer to the 1394a specification. The use of suspend/resume is recommended for new designs. The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when the /RESET input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The port twisted-pair bias voltage circuitry is disabled during power down, during reset, or when the port is disabled as commanded by the LLC. The CNA (cable-not-active) terminal provides a high output when all twisted-pair cable ports are disconnected, and can be used along with LPS to determine when to power down the PDI1394P22. The CNA output is not debounced. In Power Down mode, the CNA detection circuitry remains enabled. The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC indicates to the PHY that the LLC is powered up and active. During LLC Power Down mode, as indicated by the LPS input being low for more than 25 s, the PDI1394P22 deactivates the PHY-LLC interface to save power. The PDI1394P22 continues the necessary repeater function required for network operation during this low power state. If the PHY receives a link-on packet from another node, the C/LKON terminal is activated to output a square-wave signal. The LLC recognizes this signal, reactivates any powered-down portions of the LLC, and notifies the PHY of its power-on status via the LPS terminal. The PHY confirms notification by deactivating the square-wave signal on the C/LKON terminal, then enables the PHY-link interface. 1999 Jul 09 7 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 8.0 ABSOLUTE MAXIMUM RATINGS 1 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL VDD VI VI-5V VO PARAMETER DC supply voltage DC input voltage 5 volt tolerant input voltage range DC output voltage range at any output Human Body Model Electrostatic discharge Tamb Tstg Operating free-air temperature range Storage temperature range Machine Model 0 -65 CONDITION MIN -0.5 -0.5 -0.5 -0.5 MAX 4.0 VDD+0.5 5.5 VDD+0.5 2 200 +70 +150 UNIT V V V V kV V C C NOTE: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 9.0 RECOMMENDED OPERATING CONDITIONS SYMBOL VDD VIH VIL IOH/IOL IO VID VIC-100 C VIC-200 C VIC-100 C tPU Supply voltage High-level input voltage, pins g g, CTLn, Dn, C/LKON 2 Low-level input voltage, pins CTLn, Dn, C/LKON 2 Output current, pins CTLn, Dn, C/LKON and SYSCLK Output current Differential input voltage amplitude TPB common-mode input voltage common mode TPB common mode input voltage common-mode TPB common mode input voltage common-mode Power-up reset time Receive input jitter PARAMETER Source power node Non-source power node /ISO = VDD, VDD = 2.7 V /ISO = VDD, VDD >= 3.0 V /ISO = VDD VOH = VDD -0.5 V, VOL = 0.5 V TPBIAS outputs TPA, TPB cable inputs, during data reception TPA, TPB cable inputs, during data arbitration Speed signalling off g g or S100 speed signal S200 speed signal S400 speed signal Source power node Non-source power node Source power node Non-source power node Source power node Non-source power node -12 -6 118 168 1.165 1.165 0.935 0.935 0.523 0.523 2 1.08 0.5 0.315 0.8 0.55 0.5 24.5735 24.576 24.5785 MIN 3.0 2.7 1 2.3 2.6 TYP 3.3 3.0 MAX 3.6 3.6 5.5 5.5 0.7 12 2.5 260 265 2.515 2.015 1 2.515 2.015 1 2.515 2.015 1 UNIT V V V V V mA mA mV mV V V V V V V ms ns ns ns ns ns ns MHz Set by capacitor between /RESET pin and GND TPA, TPB cable inputs, S100 operation TPA, TPB cable inputs, S200 operation TPA, TPB cable inputs, S400 operation Between TPA and TPB cable inputs, S00 operation Receive input skew Between TPA and TPB cable inputs, S200 operation Between TPA and TPB cable inputs, S400 operation Crystal connected according to Figure 8 or external clock input at pin XI fXTAL Crystal or external clock frequency NOTES: 1. For a node that does not source power to the bus (see Section 4.2.2.2 in the IEEE 1394-1995 standard). 2. C/LKON is only an input when /RESET = 0. 1999 Jul 09 8 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 10.0 CABLE DRIVER SYMBOL VOD IO(diff) PARAMETER Differential output voltage Driver Difference current, TPA+, TPA-, TPB+, TPB- 1 TEST CONDITION 56 load Drivers enabled, speed signaling OFF 100 Mbit/s speed signaling enabled ISP VOFF Common mode speed signaling current, TPB+, TPB- 2 OFF state differential voltage 200 Mbit/s speed signaling enabled 400 Mbit/s speed signaling enabled Drivers disabled LIMITS MIN 172 -1.051 -0.81 -4.84 -12.4 TYP MAX 265 0.881 -0.44 -2.53 -8.10 20 UNIT mV mA mA mA mA mV NOTES: 1. Limits defined as algebraic sum of TPA+ and TPA- driver currents. Limits also apply to TPB+ and TPB- algebraic sum of driver currents. 2. Limits defined as absolute limit of each of TPB+ and TPB- driver currents. 11.0 CABLE RECEIVER SYMBOL ZID ZIC C VTH-R VTH-CB VTH+ VTH- VTH-SP200 VTH-SP400 ICD PARAMETER Differential input impedance Common mode input impedance Receiver input threshold voltage Cable bias detect threshold, TPBn cable inputs Positive arbitration comparator threshold voltage Negative arbitration comparator threshold voltage Speed signal threshold Speed signal threshold Connect detect output at TPBIAS pins TEST CONDITION Drivers disabled Drivers disabled Drivers disabled Drivers disabled Drivers disabled Drivers disabled TPBIAS-TPA common mode voltage, drivers disabled TPBIAS-TPA common mode voltage, drivers disabled Drivers disabled LIMITS MIN 10 20 24 -30 0.6 89 -168 49 314 30 1.0 168 -89 131 396 76 TYP 14 4 MAX UNIT k pF k pF mV V mV mV mV mV A 1999 Jul 09 9 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 12.0 OTHER DEVICE I/O SYMBOL PARAMETER Peak IDD Supply current 1 TEST CONDITION Transmit 2 Repeat 3 Idle 4 MIN TYP tbf tbf tbf tbf MAX tbf UNIT mA mA mA mA IDD-PD VTH Supply current in power down or suspend mode Cable power status threshold voltage PD = VDD in power down mode 370 k-400 k resistor between cable power and CPS pin: Measured at cable power side of resistor VDD >= 2.7 V, IOH = -4 mA, /ISO = VDD 7.5 2.2 2.8 VDD-0.4 tbf 8.5 mA V V V V 8.0 VOH High-level output voltage. pins CTL Hi h l l t t lt i CTLn, Dn, SYSCLK, CNA, C/LKON VDD >= 3.0 V, IOH = -4 mA, /ISO = VDD Annex J: IOH = -9 mA, /ISO = 0 IOL = 4 mA, /ISO = VDD Annex J: IOL = 9 mA, /ISO = 0 /ISO = VDD, VI = 0 V to VDD /ISO = VDD, VI = 0 V to VDD /ISO = 0 V; VDD = 3.6 V VO = VDD or 0 V VI = 1.5 V, PD = 0 VI = 0 V, PD = 0 VI = VDD, PD = VDD /ISO = 0 V VO OL IBH+ IBH- II IOZ IRST-UP S IRST-DN VIT+ VIT- VIT+ VIT- VO Low-level Low level output voltage Positive peak bus holder current Negative peak bus holder current Input current, pins LREQ, LPS, PD, TEST0, TEST1, PC0-PC2 Off-state current, pins CTLn, Dn, C/LKON Pullup current /RESET input current, Pulldown current, /RESET input Positive going threshold voltage, LREQ, CTL0, CTL1, D0-D7, C/LKON inputs 5 0.4 0.4 0.08 -0.25 0.25 -0.08 5 -5 -80 -90 86 VDD/2 + 0.3 VDD/2 - 0.9 -40 -45 260 5 -20 -22 450 VDD/2 + 0.9 VDD/2 - 0.3 VLREF+1 VLREF+0.2 1.665 2.015 V V mA mA A A A A A V V V V V Negative going threshold voltage, LREQ, /ISO = 0 V CTL0, CTL1, D0-D7, C/LKON inputs 5 Positive going threshold voltage, PD, LPS inputs Negative going threshold voltage, PD, LPS inputs TPBIAS output voltage /ISO = 0 V. VLREF = 0.42 x VDD /ISO = 0 V. VLREF = 0.42 x VDD At rated IO current NOTES: 1. Worst case, all ports transmitting, 100% bandwidth at S400, VDD = 3.6 V, TA = 0C: At TA = 70C, the maximum current is tbf mA. 2. All ports transmitting, 100% bandwidth at S400, VDD = 3.3 V, TA = 25C 3. Receiving on port 0 and transmitting on port 1 and port 2. Full ISO payload of 84 S, S400, data value of CCCCCCCCh, VDD = 3.3 V, TA = 25C 4. Receiving cycle starts on port 0 and transmitting cycle starts on port 1 and port 2, VDD = 3.3 V, TA = 25C 5. C/LKON is only an input when /RESET = 0 1999 Jul 09 10 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 13.0 THERMAL CHARACTERISTICS SYMBOL RjA PARAMETER Junction-to-free-air thermal resistance TEST CONDITION Board mounted, no air flow LIMITS MIN TYP TBD MAX UNIT C/W 14.0 AC CHARACTERISTICS SYMBOL Transmit jitter Transmit skew tr tf tSU tH tD TPA, TPB differential output voltage rise time TPA, TPB differential output voltage fall time Setup time, CTL0, CTL1, D1-D7, LREQ to SYSCLK Hold time, CTL0, CTL1, D1-D7, LREQ after SYSCLK Delay time SYSCLK to CTL0, CTL1, D1-D7 PARAMETER TPA, TPB Between TPA and TPB 10% to 90%; At 1394 connector 90% to 10%; At 1394 connector 50% to 50%; See Figure 2 50% to 50%; See Figure 2 50% to 50%; See Figure 3 0.5 0.5 5 0 0.5 11 CONDITION MIN TYP MAX 0.15 0.10 1.2 1.2 UNIT ns ns ns ns ns ns ns 15.0 TIMING WAVEFORMS TPAn+ TPBn+ SYSCLK 56 tD TPAn- TPBn- Dn, CTLn, LREQ SV01098 Figure 1. Test load diagram SV01100 Figure 3. Dn, CTLn, output delay relative to SYSCLK SYSCLK tSU tH Dn, CTLn, LREQ SV01099 Figure 2. Dn, CTLn, LREQ input setup and hold times 1999 Jul 09 11 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 16.0 INTERNAL REGISTER CONFIGURATION There are 16 accessible internal registers in the PDI1394P22. The configuration of the registers at addresses 0 through 7 (the base registers) is fixed, while the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected. The selected page is set in base register 7h. The configuration of the base registers is shown in Table 1, and corresponding field descriptions are given in Table 2. The base register field definitions are unaffected by the selected page number. A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables) is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved. Table 1. Base Register Configuration ADDRESS 0000 0001 0010 0011 0100 0101 0110 0111 Page_Select Rsvd L RPIE RHB IBR Extended (111b) PHY_Speed (010b) C ISBR CTOI Rsvd Rsvd Jitter (000) CPSI Reserved Port Select STOI PEI BIT POSITION 0 1 2 Physical ID Gap_Count Num_Ports (0011b) Delay (0000b) Pwr_Class EAA EMC 3 4 5 6 R 7 CPS Table 2. Base Register Field Descriptions FIELD Physical ID SIZE 6 TYPE Rd DESCRIPTION This field contains the physical address ID of this node determined during self-ID. The physical-ID is invalid after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer. Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is set to 1 during tree-ID if this node becomes root. Cable-power-status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally tied to serial bus cable power through a 370 k-410 k resistor. A 0 in this bit indicates that the cable power voltage has dropped below its threshold for ensured reliable operation. Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB bit is reset to 0 by a hardware reset, and is unaffected by a bus reset. Initiate bus reset. This bit instructs the PHY to initiate a long (166 s) bus reset at the next opportunity. Any receive or transmit operation in progress when this bit is set will complete before the bus reset is initiated. The IBR bit is reset to 0 after a hardware reset or a bus reset. Arbitration gap count. This value is used to set the subaction (fair) gap, arb-reset gap, and arb-delay times. The gap count can be set either by a write to the register, or by reception or transmission of a PHY_CONFIG packet. The gap count is reset to 3Fh by hardware reset or after two consecutive bus resets without an intervening write to the gap count register (either by a write to the PHY register or by a PHY_CONFIG packet). Extended register definition. For the PDI1394P22, this field is 111b, indicating that the extended register set is implemented. Number of ports. This field indicates the number of ports implemented in the PHY. For the PDI1394P22 this field is 3. PHY speed capability. For the PDI1394P22, this field is 010b, indicating S400 speed capability. PHY repeater data delay. This field indicates the worst case repeater data delay for this PHY, expressed as 144+(delay x 20) ns. For the PDI1393P21, this field is 0. Link active status. This bit indicates that this node's link is active. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. This bit is set to 1 by a hardware reset and is unaffected by a bus reset. Contender status. This bit indicates that this node is a contender for the bus or isochronous resource manager. This bit is replicated in the "c" field (bit 20) of the self-ID packet. This bit is set to the state specified by the C/LKON input terminal by a hardware reset and is unaffected by a bus reset. PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest repeater data delay, expressed as (Jitter + 1) x 20 ns. For the PDI1394P22, this field is 0. R CPS 1 1 Rd Rd RHB IBR 1 1 Rd/Wr Rd/Wr Gap_Count 6 Rd/Wr Extended Num_Ports PHY_Speed Delay L 3 4 3 4 1 Rd Rd Rd Rd Rd/Wr C 1 Rd/Wr Jitter 3 Rd 1999 Jul 09 12 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 FIELD Pwr_Class SIZE 3 TYPE Rd/Wr DESCRIPTION Node power class. This field indicates this node's power consumption and source characteristics and is replicated in the pwr field (bits 21-23) of the self-ID packet. This field is reset to the state specified by the PC0-PC2 input terminals upon hardware reset, and is unaffected by a bus reset. See Table 18. Resuming port interrupt enable. This bit, if set to 1, enables the port event interrupt (PEI) bit to be set whenever resume operations begin on any port. This bit is reset to 0 by hardware reset and is unaffected by bus reset. Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3 s) arbitrated bus reset at the next opportunity. This bit is reset to 0 by a bus reset. NOTE: Legacy IEEE Std 1394-1995 compliant PHYs are not capable of performing short bus resets. Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus reset being performed. RPIE 1 Rd/Wr ISBR 1 Rd/Wr CTOI 1 Rd/Wr Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times-out during tree-ID start, and may indicate that the bus is configured in a loop. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. NOTE: If the network is configured in a loop, only those nodes which are part of the loop should generate a configuration time out interrupt. All other nodes should instead time out waiting for the tree-ID and/or self-ID process to complete and then generate a state time-out interrupt and bus-reset. CPSI 1 Rd/Wr Cable-power-status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low indicating that cable power may be too low for reliable operation. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. State time-out interrupt. This bit indicates that a state time-out has occurred. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. Port event interrupt. This bit is set to 1 on any change in the connected, bias, disabled, or fault bits for any port for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt enable (RPIE) bit is set, the PEI bit is set to 1 at the start of resume operations on any port. This bit is reset to 0 by hardware reset, or by writing a 1 to this register bit. Enable arbitration acceleration. This bit enables the PHY to perform the various arbitration acceleration enhancements defined in P1394a (ACK-accelerated arbitration, asynchronous fly-by concatenation, and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is unaffected by bus reset. NOTE: The EAA bit should be set only if the attached LLC is P1394a compliant. If the LLC is not P1394a compliant, use of the arbitration acceleration enhancements can interfere with isochronous traffic by excessively delaying the transmission of cycle-start packets. STOI PEI 1 1 Rd/Wr Rd/Wr EAA 1 Rd/Wr EMC 1 Rd/Wr Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of differing speeds in accordance with the protocols defined in P1394a. This bit is reset to 0 by hardware reset and is unaffected by bus reset. NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy IEEE Std 1394-1995 PHYs. However, use of multispeed concatenation requires that the attached LLC be P1394a compliant. Page_Select Port_Select 3 4 Rd/Wr Rd/Wr Page_Select. This field selects the register page to use when accessing register addresses 8 through 15. This field is reset to 0 by a hardware reset and is unaffected by bus-reset. Port_Select. This field selects the port when accessing per-port status or control (e.g., when one of the port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset to 0 by hardware reset and is unaffected by bus reset. 1999 Jul 09 13 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 The Port Status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. The configuration of the port status page registers is shown in Table 3 and corresponding field descriptions given in Table 4. If the selected port is unimplemented, all registers in the port status page are read as 0. Table 3. Page 0 (Port Status) Register Configuration ADDRESS 1000 1001 1010 1011 1100 1101 1110 1111 BIT POSITION 0 AStat Peer_Speed 1 2 BStat PIE Reserved Reserved Reserved Reserved Reserved Reserved 3 4 Ch Fault 5 Con 6 Bias Reserved 7 Dis Table 4. Page 0 (Port Status) Register Field Descriptions FIELD AStat SIZE 2 TYPE Rd Code 11 01 10 00 BStat Ch 2 1 Rd Rd Arb Value Z 1 0 invalid DESCRIPTION TPA line state. This field indicates the TPA line state of the selected port, encoded as follows: TPB line state. This field indicates the TPB line state of the selected port. This field has the same encoding as the ASTAT field. Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected port is the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch bit is invalid after a bus-reset until tree-ID has completed. Debounced port connection status. This bit indicates that the selected port is connected. The connection must be stable for the debounce time of 330ms-350ms for the Con bit to be set to 1. The Con bit is reset to 0 by hardware reset and is unaffected by bus reset. NOTE: The Con bit indicates that the port is physically connected to a peer PHY, but the port is not necessarily active. Con 1 Rd Bias 1 Rd Debounced incoming cable bias status. A 1 indicates that the selected port is detecting incoming cable bias. The incoming cable bias must be stable for the debounce time of 41.6s-52s for the Bias bit to be set to 1. Port disabled control. If 1, the selected port is disabled. The Dis bit is reset to 0 by hardware reset (all ports are enabled for normal operation following hardware reset). The Dis bit is not affected by bus reset. Port peer speed. This field indicates the highest speed capability of the peer PHY connected to the selected port, encoded as follows: Code 000 001 010 011-111 Peer Speed S100 S200 S400 invalid Dis 1 Rd/Wr Peer_Speed 3 Rd The Peer_Speed field is invalid after a bus reset until self-ID has completed. NOTE: Peer speed codes higher than 010b (S400) are defined in P1394a. However, the PDI1394P22 is only capable of detecting peer speeds up to S400. PIE 1 Rd/Wr Port event interrupt enable. When set to 1, a port event on the selected port will set the port event interrupt (PEI) bit and notify the link. this bit is reset to 0 by a hardware reset, and is unaffected by bus-reset. Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port, and that the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming cable bias from its attached peer. A suspend-fault occurs when a suspending port continues to detect incoming cable bias from its attached peer. Writing 1 to this bit clears the fault bit to 0. This bit is reset to 0 by hardware reset and is unaffected by bus reset. 14 Fault 1 Rd/Wr 1999 Jul 09 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 The Vendor Identification page is used to identify the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select field in base register 7. The configuration of the Vendor Identification page is shown in Table 5, and corresponding field descriptions are given in Table 6. Table 5. Page 1 (Vendor ID) Register Configuration ADDRESS 1000 1001 1010 1011 1100 1101 1110 1111 BIT POSITION 0 1 2 3 Compliance Reserved Vendor_ID[0] Vendor_ID[1] Vendor_ID[2] Product_ID[0] Product_ID[1] Product_ID[2] 4 5 6 7 Table 6. Page 1 (Vendor ID) Register Field Descriptions FIELD Compliance Vendor_ID Product_ID SIZE 8 24 24 TYPE Rd Rd Rd DESCRIPTION Compliance level. For the PDI1394P22, this field is 01h, indicating compliance with the P1394a specification. Manufacturer's organizationally unique identifier (OUI). For the PDI1394P22, this field is 00_06_37h (Philips Semiconductors) (the MSB is at register address 1010b). Product identifier. For the PDI1394P22, this field is 43_11_00h (the MSB is at register address 1101b). 1999 Jul 09 15 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 17.0 APPLICATION INFORMATION CPS PDI1394P21 TPBIAS 400K 0.3-1.0 F CABLE POWER PAIR 56 TPAn+ TPAn- 56 CABLE PAIR A CABLE PORT TPBn+ TPBn- 56 56 CABLE PAIR B 220pF 5 k OUTER SHIELD TERMINATION SV01744 The IEEE Std 1394-1995 calls for a 250 pF capacitor, which is a non-standard component value. A 220 pF capacitor is recommended. Figure 4. Twisted pair cable interface connections OUTER CABLE SHIELD 1 M 0.01 F 0.001 F CHASSIS GROUND SV01748 Figure 5. Typical outer shield termination 1 k LINK POWER 3 0.001 F SQUARE WAVE INPUT 0.1 F 6 DVDD 1 k VDD LPS DGND LPS SV01781 Use one of these networks per side for all digital power and ground pins and one per side for all analog power and ground pins. Place the network as close to the PHY as possible. Figure 6. Power supply decoupling network SV01750 Figure 7. Non-isolated connection variations for LPS 1999 Jul 09 16 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 17.1 External Component Connections VDD 12 pF 12 pF 6.34 k 1% 24.576 MHz 0.1 F 0.001 F 0.1 F 64 DGND 63 SYSCLK 62 DVDD 61 /RESET 60 XO 59 XI 58 PLLGND 57 PLLVDD 56 DGND 55 R1 54 R0 53 AGND 52 AGND 51 AVDD 50 AVDD 49 AGND 0.3-1.0 F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CNA OUT LINK PULSE OR VDD REFER TO FIGURE 7 15 16 LREQ DGND CTL0 CTL1 D0 D1 DVDD D2 D3 D4 D5 D6 D7 DGND CNA LPS C/LKON TEST1 TEST0 DGND DVDD DVDD DVDD AVDD AVDD AGND TPBIAS2 TPA2+ TPA2- TPB2+ TPB2- AVDD TPBIAS1 TPA1+ 48 47 46 45 44 43 42 41 40 TPBIAS TP CABLES INTERFACE CONNECTION 0.3-1.0 F TPBIAS PDI1394P22 TPA1- TP CABLES INTERFACE CONNECTION 0.3-1.0 F TPB1+ 39 TPB1- TPBIAS0 TPA0+ TPA0- 38 37 36 35 TP CABLES INTERFACE CONNECTION TPBIAS TPB0+ 34 TPB0- 33 17 18 PD CPS /ISO PC0 PC1 PC2 19 POWER DOWN 20 21 22 23 /ISO 24 25 26 27 28 29 30 31 32 POWER CLASS PROGRAMMING 10 k LKON 370- 410 k CABLE POWER BUS MANAGER SV001783 See Figure 6 for recommended power and ground connections. Figure 8. External Component Connections 1999 Jul 09 17 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 17.2 Using the PDI1394P22 with a non-P1394a link layer The PDI1394P22 implements the PHY-LLC interface specified in the P1394a Supplement. This interface is based upon the interface described in informative Annex J of IEEE Std 1394-1995, which is the interface used in older PHY devices. The PHY-LLC interface specified in P1394a is completely compatible with the older Annex J interface. The P1394a Supplement includes enhancements to the Annex J interface that must be comprehended when using the PDI1394P22 with a non-P1394a LLC device. 17.3 /Reset and Power Down Forcing the /RESET pin low causes a Bus Reset condition on the active cable ports, and resets the internal logic to the Reset Start state. SYSCLK remains active. For power-up (and after Power Down is asserted) /RESET must be asserted low for a minimum of 2 ms from the time that the PHY power reaches the minimum required supply voltage. This is required to assure proper PLL operation before the PHY begins using the clock. An internal pull-up resistor is connected to VDD, so only an external delay capacitor is required. When using a passive capacitor on the /RESET terminal to generate a power-on reset signal, the minimum value of 0.1 F and also satisfies the following equation: Cmin = 0.0077 x T + 0.085 where Cmin is the minimum capacitance on the /RESET terminal in F, and T is the VDD ramp time, 10%-90%, in ms. Additionally, an approximately 120 k resistor should be connected in parallel with the reset capacitor from the /RESET terminal to GND to ensure that the capacitor is discharged when PHY power is removed. An alternative to the passive reset is to actively drive /RESET low for the minimum reset time following power on. This input is a standard logic buffer and may also be driven by an open drain logic output buffer. The /RESET pin also has a n-channel pull-down transistor activated by the Power Down pin. For a reset during normal operation, a 10 us low pulse on this pin will accomplish a full PHY reset. This pulse, as well as the 2 ms power up pulse, could be microprocessor controlled, in which case the external delay capacitor would not be needed. For more details on using single capacitor isolation with this pin, please refer to the Philips Isolation Application Note AN2452 The Power Down input powers down all device functions with the exception of the CNA circuit to conserve power in portable or battery-powered applications. It must be held high for at least 3.5 ms to assure a successful reset after power down. This pin is equipped with Bus Hold circuitry and supports an optional isolation barrier. * A new LLC service request was added which allows the LLC to temporarily enable and disable asynchronous arbitration accelerations. If the LLC does not implement this new service request, the arbitration enhancements should not be enabled (see the EAA bit in PHY register 5). * The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not support multispeed concatenation, multispeed concatenation should not be enabled in the PHY (see the EMC bit in PHY register 5). * In order to accommodate the higher transmission speeds expected in future revisions of the standard, P1394a extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus request from 7 bits to 8 bits. The new speed codes were carefully selected so that new P1394a PHY and LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices that use the 2-bit speed codes. The PDI1394P22 correctly interprets both 7-bit bus requests (with 2-bit speed code) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately followed by another request (e.g., a register read or write request), the PDI1394P22 correctly interprets both requests. Although the PDI1394P22 correctly interprets 8-bit bus requests, a request with a speed code exceeding S400 results in the PDI1394P22 transmitting a null packet (data-prefix followed by data-end, with no data in the packet). 1999 Jul 09 18 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 18.0 PRINCIPLES OF OPERATION The PDI1394P22 is designed to operate with an LLC such as the Philips Semiconductors PDI1394L11 or PDI1394L21. The following paragraphs describe the operation of the PHY-LLC interface. The interface to the LLC consists of the SYSCLK, CTL0-CTL1, D0-D7, LREQ, LPS, C/LKON, and /ISO terminals on the PDI1394P22 as shown in Figure 9. terminals are used for data transfer. When the PDI1394P22 is in control of the D0-D7 bus, unused Dn terminals are driven low during S100 and S200 operations. When the LLC is in control of the D0-D7 bus, unused Dn terminals are ignored by the PDI1394P22. The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access to the serial bus for packet transmission, read or write PHY registers, or control arbitration acceleration. The LPS and C/LKON terminals are used for power management of the PHY and LLC. The LPS terminal indicates the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable SYSCLK. The C/LKON terminal is used to send a wake-up notification to the LLC and to indicate an interrupt to the LLC when either LPS is inactive or the PHY register L bit is zero. The /ISO terminal is used to enable the output differentiation logic on the CTL0-CTL1 and D0-D7 terminals. Output differentiation is required when an isolation barrier of the type described in Annex J of IEEE Std 1394-1995 is implemented between the PHY and LLC. The PDI1394P22 normally controls the CTL0-CTL1 and D0-D7 bidirectional buses. The LLC is allowed to drive these buses only after the LLC has been granted permission to do so by the PHY. SV01757 PDI1394P21 SYSCLK LINK LAYER CONTROLLER CTL0-CTL1 D0-D7 LREQ LPS C/LKON /ISO /ISO /ISO Figure 9. PHY-LLC interface The SYSCLK terminal provides a 49.152 MHz interface clock. all control and data signals are synchronized to, and sampled on, the rising edge of SYSCLK. The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data between the PDI1394P22 and LLC. The D0-D7 terminals form a bidirectional data bus, which is used to transfer status information, control information, or packet data between the devices. The PDI1394P22 supports S100, S200, and S400 data transfers over the D0-D7 data bus. In S100 operation only the D0 and D1 terminals are used; in S200 operation only the D0-D3 terminals are used; and in S400 operation all D0-D7 There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data transmit, and data receive. The LLC issues a service request to read or write a PHY register, to request the PHY to gain control of the serial bus in order to transmit a packet, or to control arbitration acceleration. The PHY may initiate a status transfer either autonomously or in response to a register read request from the LLC. The PHY initiates a receive operation whenever a packet is received from the serial bus. The PHY initiates a transmit operation after winning control of the serial-bus following a bus request by the LLC. The transmit operation is initiated when the PHY grants control of the interface to the LLC. The encoding of the CTL0-CTL1 bus is shown in Table 7 and Table 8. Table 7. CTL encoding when PHY has control of the bus CTL0 0 0 1 1 CTL1 0 1 0 1 Idle Status Receive Grant NAME No activity (this is the default mode) Status information is being sent from the PHY to the LLC An incoming packet is being sent from the PHY to the LLC The LLC has been given control of the bus to send an outgoing packet DESCRIPTION Table 8. CTL encoding when LLC has control of the bus CTL0 0 0 1 1 CTL1 0 1 0 1 NAME Idle Hold Transmit Reserved DESCRIPTION The LLC releases the bus (transmission has been completed) The LLC is holding the bus while data is being prepared for transmission, or indicating that another packet is to be transmitted (concatenated) without arbitrating An outgoing packet is being sent from the LLC to the PHY None 1999 Jul 09 19 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 LR0 LR1 LR2 LR3 LR(n-2) LR(n-1) SV01758 Figure 10. LREQ Request Stream 18.1 LLC service request To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the LLC sends a serial bit stream on the LREQ terminal as shown in Figure 10. The length of the stream will vary depending on the type of request as shown in Table 9. For a bus request the length of the LREQ bit stream is 7 or 8 bits, as shown in Table 11. Table 11. Bus Request BIT(S) 0 1-3 NAME Start Bit Request Type Request Speed DESCRIPTION Indicates the beginning of the transfer (always 1). Indicates the type of bus request. See Table 10. Indicates the speed at which the PHY will send the data for this request. See Table 12 for the encoding of this field. Indicates the end of the transfer (always 0). If bit 6 is 0, this bit may be omitted. Table 9. Request Stream Bit Length REQUEST TYPE Bus request Read register request Write register request Acceleration control request NUMBER OF BITS 7 or 8 9 17 6 4-6 7 Stop Bit Regardless of the type of request, a start bit of 1 is required at the beginning of the stream, and a stop bit of 0 is required at the end of the stream. The second through fourth bits of the request stream indicate the type of the request. In the descriptions below, bit 0 is the most significant, and is transmitted first in the request bit stream. The LREQ terminal is normally low. Encoding for the request type is shown in Table 10. The 3-bit request speed field used in bus requests is shown in Table 12. Table 12. Bus Request Speed Encoding LR4-LR6 000 010 100 All others DATA RATE S100 S200 S400 Invalid Table 10. Request Type Encoding LR1-LR3 000 NAME ImmReq DESCRIPTION Immediate bus request. Upon detection of idle, the PHY takes control of the bus immediately without arbitration Isochronous bus request. Upon detection of idle, the PHY arbitrates for the bus without waiting for a subaction gap. Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol. Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol The PHY returns the specified register contents through a status transfer. Write to the specified register. Enable or disable asynchronous arbitration acceleration. Reserved. 20 001 IsoReq NOTE: The PDI1394P22 will accept a bus request with an invalid speed code and process the bus request normally. However, during packet transmission for such a request, the PDI1394P22 will ignore any data presented by the LLC and will transmit a null packet. For a read register request, the length of the LREQ bit stream is 9 bits as shown in Table 13. 010 PriReq Table 13. Read Register Request BIT(S) 0 1-3 4-7 8 NAME Start Bit Request Type Address Stop Bit DESCRIPTION Indicates the beginning of the transfer (always 1). A 100 indicating this is a read register request. Identifies the address of the PHY register to be read. Indicates the end of the transfer (always 0). 011 FairReq 100 RdReg 101 110 111 1999 Jul 09 WrReg AccelCtl Reserved Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 14. Table 14. Write Register Request BIT(S) 0 1-3 4-7 8-15 16 NAME Start Bit Request Type Address Data Stop Bit DESCRIPTION Indicates the beginning of the transfer (always 1). A 101 indicating that this is a write register request. Identifies the address of the PHY register to be written to. Gives the data that is to be written to the specified register address. Indicates the end of the transfer (always 0). end of the received packet and the start of the transmitted acknowledge packet. As soon as the receive packet ends, the PHY immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant to send another type of packet. After the interface is released, the LLC may proceed with another request. The LLC may request only one bus request at a time. Once the LLC issues any request for bus access (ImmReq, IsoReq, FairReq, or PriReq), it cannot issue another request until the PHY indicates that the bus request was "lost" (bus arbitration lost and another packet received), or "won" (bus arbitration won and the LLC granted control). The PHY ignores new bus requests while a previous bus request is pending. All bus requests are cleared upon a bus reset. For write register requests, the PHY loads the specified data into the addressed register as soon as the request transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the LLC at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the PHY continues to attempt the transfer of the requested register until it is successful. A write or read register request may be made at any time, including while a bus request is pending. Once a read register request is made, the PHY ignores further read register requests until the register contents are successfully transferred to the LLC. A bus reset does not clear a pending read register request. The PDI1394P22 includes several arbitration acceleration enhancements which allow the PHY to improve bus performance and throughput by reducing the number and length of inter-packet gaps. These enhancements include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following acknowledge packets. Then enhancements are enabled when the EAA bit in PHY register 5 is set. The arbitration acceleration enhancements may interfere with the ability of the cycle master node to transmit the cycle start packet under certain circumstances. The acceleration control request is therefore provided to allow the LLC to temporarily enable or disable the arbitration acceleration enhancements of the PDI1394P22 during the asynchronous period. The LLC typically disables the enhancements when its internal cycle counter rolls over indicating that a cycle start packet is imminent, and then re-enables the enhancements when it receives a cycle start packet. The acceleration control request may be made at any time, however, and is immediately serviced by the PHY. Additionally, a bus reset or isochronous bus request will cause the enhancements to be re-enabled, if the EAA bit is set. For an acceleration control request, the length of the LREQ data stream is 6 bits as shown in Table 15. Table 15. Acceleration Control Request BIT(S) 0 1-3 4 NAME Start Bit Request Type Control DESCRIPTION Indicates the beginning of the transfer (always 1). A 110 indicating this is an acceleration control request. Asynchronous period arbitration acceleration is enabled if 1, and disabled if 0. Indicates the end of the transfer (always 0). 5 Stop Bit For fair or priority access, the LLC sends the bus request (FairReq or PriReq) at least one clock after the PHY-LLC interface becomes idle. If the CTL terminals are asserted to the receive state (10b) by the PHY, then any pending fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or priority requests if the Receive state is asserted while the LLC is sending the request. The LLC may then reissue the request one clock after the next interface idle. The cycle master node uses priority bus request (PriReq) to send a cycle start packet. After receiving or transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY will clear an isochronous request only when the bus has been won. To send an acknowledge packet, the link must issue an immediate bus request (ImmReq) during the reception of the packet addressed to it. This is required in order to minimize the idle gap between the 1999 Jul 09 21 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 18.2 Status transfer A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. The PHY waits until the interface is idle before starting the transfer. The transfer is initiated by the PHY asserting Status (01b) on the CTL terminals, along with the first two bits of status information on the D[0:1] terminals. The PHY maintains CTL = Status for the duration of the status transfer. The PHY may prematurely end a status transfer by asserting something other than Status on the CTL terminals. This occurs if a packet is received before the status transfer completes. The PHY continues to attempt to complete the transfer until all status information has been successfully transmitted. There is at least one idle cycle between consecutive status transfers. The PHY normally sends just the first four bits of status to the LLC. These bits are status flags that are needed by the LLC state machines. The PHY sends an entire 16-bit status packet to the LLC after a read register request, or when the PHY has pertinent information to send to the LLC or transaction layers. The only defined condition where the PHY automatically sends a register to the LLC is after self-ID, where the PHY sends the physical-ID register that contains the new node address. All status transfers are either 4 or 16 bits unless interrupted by a received packet. The status flags are considered to have been successfully transmitted to the LLC immediately upon being sent, even if a received packet subsequently interrupts the status transfer. Register contents are considered to have been successfully transmitted only when all 8 bits of the register have been sent. A status transfer is retried after being interrupted only if any status flags remain to be sent, or if a register transfer has not yet completed. The definition of the bits in the status transfer is shown in Table 16, and the timing is shown in Figure 11. The sequence of events for a status transfer is as follows: * Status transfer initiated. the PHY indicates a status transfer by asserting status on the CTL lines along with the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle). Normally (unless interrupted by a receive operation), a status transfer will be either 2 or 8 cycles long. A 2-cycle (4 bit) transfer occurs when only status information is to be sent. An 8-cycle (16 bit) transfer occurs when register data is to be sent in addition to any status information. * Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL lines. If a bus reset is pending, the PHY may also assert Grant on the CTL line immediately following a complete status transfer. Table 16. Status Bits BIT(S) 0 1 2 3 4-7 8-15 NAME Arbitration Reset Gap Subaction gap Bus reset Interrupt Address Data DESCRIPTION Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as defined in the IEEE 1394-1995 standard). This bit is used by the LLC in the busy/retry state machine. Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in the IEEE 1394-1995 standard). This bit is used by the LLC to detect the completion of an isochronous cycle. Indicates that the PHY has entered the bus reset state. Indicates that a PHY interrupt event has occurred. An interrupt event may be a configuration time-out, a cable-power voltage falling too low, a state time-out, or a port status change. This field holds the address of the PHY register whose contents are being transferred to the LLC. This field holds the register contents. SYSCLK (a) (b) 00 CTL0, CTL1 00 01 01 D0, D1 00 S[0:1] S[14:15] 00 SV01759 Figure 11. Status Transfer Timing 1999 Jul 09 22 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 18.3 Receive Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting Receive on the CTL terminals and a logic 1 on each of the D terminals ("data-on" indication). The PHY indicates the start of a packet by placing the speed code (encoded as shown in Table 17) on the D terminals, followed by packet data. The PHY holds the CTL terminals in the Receive state until the last symbol of the packet has been transferred. The PHY indicates the end of packet data by asserting Idle on the CTL terminals. All received packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not included in the calculation of CRC or any other data protection mechanisms. PDI1394P22 sends at least one "data-on" indication before sending the speed code or terminating the receive operation. The PDI1394P22 also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization to the LLC. This packet is transferred to the LLC just as any other received self-ID packet. The sequence of events for a normal packet reception is as follows: * Receive operation initiated. The PHY indicates a receive Table 17. Speed Code for the Receiver D0-D7 0000 0000 0100 0000 0101 0000 1111 1111 DATA RATE S100 S200 S400 "data-on" indication operation by asserting Receive on the CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a status transfer operation that is in progress so that the CTL lines may change from status to receive without an intervening idle. * Data-on indication. The PHY may assert the data-on indication code on the D lines for one or more cycles preceding the speed code. * Speed code. the PHY indicates the speed of the received packet by asserting a speed code on the D lines for one cycle immediately preceding packet data. The link decodes the speed code on the first Receive cycle for which the D lines are not the data-on code. If the speed code is invalid, or indicates a speed higher than that which the link is capable of handling, the link should ignore the subsequent data. It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any data. In this case, the PHY will assert Receive on the CTL terminals with the "data-on" indication (all 1's) on the D terminals, followed by Idle on the CTL terminals, without any speed code or data being transferred. In all cases, in normal operation, the * Receive data. Following the data-on indication (if any) and the speed code, the PHY asserts packet data on the D lines with receive on the CTL lines for the remainder of the receive operation. * Receive operation terminated. The PHY terminates the receive operation by asserting the idle on the CTL lines. The PHY asserts at least one cycle of idle following a receive operation. SYSCLK (a) 00 CTL0, CTL1 01 (b) (c) D0-D7 XX FF ("data-on") SPD (d) d0 dn 00 10 00 (e) SV01760 NOTE: SPD = Speed code; see Table 17; d0-dn = Packet data. Figure 12. Normal Packet Reception Timing 1999 Jul 09 23 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 The sequence of events for a null packet reception is as follows: * Receive operation initiated. The PHY indicates a receive * Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles. operation by asserting receive on the CTL lines. Normally, the interface is idle when receive is asserted. However, the receive operation may interrupt a status transfer operation that is in progress so that the CTL lines may change from status to receive without an intervening idle. * Receive operation terminated. The PHY terminates the receive operation by asserting Idle on the CTL lines. The PHY shall assert at least one cycle of Idle following a receive operation. SYSCLK (a) 00 CTL0, CTL1 01 10 (b) 00 (c) D0-D7 XX FF ("data-on") 00 SV01761 Figure 13. Null Packet Reception Timing 1999 Jul 09 24 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 18.4 Transmit When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. If the PHY wins arbitration for the serial bus, the PHY-LLC interface bus is granted to the link by asserting the Grant state (11b) on the CTL terminals for one SYSCLK cycle, followed by Idle for one clock cycle. The LLC then takes control of the bus by asserting either Idle (00b), Hold (01b), or Transmit (10b) on the CTL terminals. Unless the LLC is immediately releasing the interface, the link may assert the Idle state for at most one clock before it must assert either Hold or Transmit on the CTL terminals. The Hold state is used by the LLC to retain control of the bus while it prepares data for transmission. The LLC may assert Hold for zero or more clock cycles (i.e., the LLC need not assert Hold before Transmit). The PHY asserts data-prefix on the serial bus during this time. When the LLC is ready to send data, the LLC asserts Transmit on the CTL terminals as well as sending the first bits of packet data on the D lines. The Transmit state is held on the CTL terminals until the last bits of data have been sent. The LLC then asserts either Hold or Idle on the CTL terminals for one clock cycle and then asserts Idle for one additional cycle before releasing the interface bus and putting the CTL and D terminals in a high-impedance state. The PHY then regains control of the interface bus. The Hold state asserted at the end of packet transmission indicates to the PHY that the LLC requests to send another packet (concatenated packet) without releasing the serial bus. The PHY responds to this concatenation request by waiting the required minimum packet separation time and then asserting Grant as before. This function may be used to send a unified response after sending an acknowledge, or to send consecutive isochronous packets during a single isochronous period. Unless multi-speed concatenation is enabled, all packets transmitted during a single bus ownership must be of the same speed (since the speed of the packet is set before the first packet). If multi-speed concatenation is enabled (when the EMSC bit of PHY register 5 is set), the LLC must specify the speed code of the next concatenated packet on the D terminals when it asserts Hold on the CTL terminals at the end of a packet. The encoding for this speed code is the same as the speed code that precedes received packet data as given in Table 17. After sending the last packet for the current bus ownership, the LLC releases the bus by asserting Idle on the CTL terminals for two clock cycles. The PHY begins asserting Idle on the CTL terminals one clock after sampling Idle from the link. Note that whenever the D and CTL terminals change direction between the PHY and the LLC, there is an extra clock period allowed so that both sides of the interface can operate on registered versions of the interface signals. The sequence of events for a normal packet transmission is as follows: * Transmit operation initiated. The PHY asserts grant on the CTL lines followed by Idle to hand over control of the interface to the link so that the link may transmit a packet. The PHY releases control of the interface (i.e., it 3-States the CTL and D outputs) following the idle cycle. * Optional idle cycle. The link may assert at most one idle cycle preceding assertion of either hold or transmit. This idle cycle is optional; the link is not required to assert Idle preceding either hold or transmit. * Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of transmit. These hold cycle(s) are optional; the link is not required to assert hold preceding transmit. * Transmit data. When data is ready to be transmitted, the link asserts transmit on the CTL lines along with the data on the D lines. * Transmit operation terminated. The transmit operation is terminated by the link asserting hold or idle on the CTL lines the link asserts hold to indicate that the PHY is to retain control of the serial bus in order to transmit a concatenated packet. the link asserts idle to indicate that packet transmission is complete and the PHY may release the serial bus. The link then asserts Idle for one more cycle following this cycle of hold or idle before releasing the interface and returning control the the PHY. * Concatenated packet speed-code. If multi-speed concatenation is enabled in the PHY, the link shall assert a speed-code on the D lines when it asserts Hold to terminate packet transmission. This speed-code indicates the transmission speed for the concatenated packet that is to follow. The encoding for this concatenated packet speed-code is the same as the encoding for the received packet speed-code (see Table 17). the link may not concatenate an S100 packet onto any higher speed packet. * After regaining control of the interface, the PHY shall assert at least one cycle of idle before any subsequent status transfer, receive operation, or transmit operation. SYSCLK (a) (b) (c) (d) 00 00 11 00 00 01 10 01 (f) 00 00 00 d0, d1, ... dn SPD 00 00 00 00 (e) (g) CTL0, CTL1 D0-D7 Link Controls Ctl and D PHY High-impedance Ctl and D Outputs SV01762 NOTE: SPD = Speed code; see Table 17; d0-dn = Packet data. Figure 14. Normal Packet Transmission Timing 1999 Jul 09 25 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 The sequence of events for a cancelled/null packet transmission is as follows: * Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of idle on the CTL lines and then releasing the interface and returning control to the PHY. Note that the link may assert Idle for a total of 3 consecutive cycles if it asserts the optional first idle cycle but does not assert hold. It is recommended that the link assert 3 cycles of Idle to cancel a packet transmission if no hold cycles are asserted. This ensures that either the link or PHY controls the interface in all cycles. * Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the interface to the link. * Optional Idle cycle. The link may assert at most one idle cycle preceding assertion of hold. This idle cycle is optional; the link is not required to assert idle preceding Hold. * Optional Hold cycles. The link may assert Hold for up to 47 cycles preceding assertion of idle. These hold cycle(s) are optional; the link is not required to assert hold preceding Idle. * After regaining control of the interface, the PHY shall assert at least one cycle of Idle before any subsequent status transfer, receive operation, or transmit operation. SYSCLK (a) (b) (c) (d) (e) CTL0, CTL1 00 11 00 00 01 00 00 D0-D7 00 00 00 Link Controls Ctl and D PHY High-impedance Ctl and D Outputs SV01763 Figure 15. Cancelled/Null Packet Transmission 19.0 POWER-CLASS PROGRAMMING The PC0-PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21-23) of the transmitted self-ID packet. Descriptions of the various power-classes are given in Table 18. The default power-class value is loaded following a hardware reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4. Table 18. Power Class Descriptions PC0-PC2 000 001 010 011 100 101 110 111 DESCRIPTION Node does not need power and does not repeat power. Node is self powered, and provides a minimum of 15 W to the bus. Node is self powered, and provides a minimum of 30 W to the bus. Node is self powered, and provides a minimum of 45 W to the bus. Node may be powered from the bus and is using up to 3 W. Node is powered from the bus and uses up to 3 W. No additional power is needed to enable the link. Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link. Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link. 1999 Jul 09 26 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 1999 Jul 09 27 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 LQFP64: plastic low profile quad flat package; 64 leads; body 7 x 7 x 1.4 mm SOT414-1 1999 Jul 09 28 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 NOTES 1999 Jul 09 29 Philips Semiconductors Objective specification 3-port physical layer interface PDI1394P22 Data sheet status Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Production [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 08-99 Document order number: 9397-750-06383 Philips Semiconductors 1999 Jul 09 30 |
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